Belkin XM Commander Especificaciones Pagina 87
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REF: BB_SRM_xM BeagleBoard-xM System
Reference Manual
Revision A2
Page 87 of 164
8.17 DVI-D Interface
The LCD interface on the processor is accessible from the DVI-D interface connector on
the board. Figure 44 is the DVI-D interface design.
R95 RES_0_0402,DNI
R92
4.7K
R96 RES_0_0402,DNI
RP1F 106 11
R97 RES_0_0402,DNI
AUX_3V3
TVDD
RP2C 103 14
RP2E 105 12
RP2D 104 13
R94 10K
RP2F 106 11
DVI_DATA19
R43
10K
DVI_UP3
AUX_3V3
Insures that the
DVI-D i s
powered down
at powerup.
R93
10K
U5B
SN74LVC2G07DBVR
3 4
RP4E 105 12
RP4F 106 11
RP4H 108 9
RP4G 107 10
AUX_3V3
MSEN
C153 0.1uF,10V
t
RT1
PTC_RXEF010
C154 0.1uF,10V
AUX_3V3
DVI_DATA20
DC_5V
VIO_1V8
R89
4.7K
RP7H 108 9
RP7C 103 14
RP7F 106 11
RP7D 104 13
RP7G 107 10
RP7E 105 12
DVI_DATA21
RP1A 101 16
R91
1K
DDC_I2C3_SCL
DVI_DATA0
RP2H 108 9
I2C3_SCL4
C156 0.1uF,10V
VIO_1V8
DVI_DATA22
RP4A 101 16
RP3A 101 16
RP3C 103 14
RP3B 102 15
RP3E 105 12
RP3D 104 13
RP3G 107 10
RP3F 106 11
RP3H 108 9
DVI_DATA1
R88
1K
I2C3_SDA4
DVI_DATA2
U11
TFP410
PD0
63
PD1
62
PD2
61
PD3
60
PD4
59
PD5
58
PD6
55
PD7
54
PD8
53
PD9
52
PD10
51
PD11
50
PD12
47
PD13
46
PD14
45
PD15
44
PD16
43
PD17
42
PD18
41
PD19
40
PD20
39
PD21
38
PD22
37
PD23
36
TXD0+
25
TXD 0-
24
TXD1+
28
TXD 1-
27
TXD2+
31
TXD 2-
30
TFADJ
19
TXC+
22
TXC-
21
DK2
7
DK1
8
IDCK+
57
IDCK-
56
DE
2
VSY N C
5
HSYNC
4
BSEL/ SCL
15
DSEL/SDA
14
HTPLG
9
NC
49
RSVD 2
34
DKEN
35
VREF
3
TGND
32
TGND
26
TGND
20
DVDD
33
DVDD
12
DGND
16
PGND
17
PVDD
18
TVDD
23
TVDD
29
DGND
48
MSE N
11
DK3
6
ISEL/RESET
13
PD
10
DVDD
1
DGND
64
TP
65
DDC_I2C3_SDA
I2C3_SCL
R84
8.45K_1%_0603
DVI_DATA3
I2C3_SDA
RP1B 102 15
R8 5 8.06K_1%_0603
DVI_DATA4
DVI_DATA23
DVI_DATA5
RP4B 102 15
RP4C 103 14
RP4D 104 13
RP2G 107 10
RP5B 102 15
RP5A 101 16
RP5D 104 13
RP5C 103 14
RP5F 106 11
RP5E 105 12
DVI_DEN
DVI_DATA10
DVI_+5v
VIO_1V8
DVI_DATA16
BSEL
TXD0-
ISEL
TXD 2+
DVI_CLK+
R86 10K
U12
TXS0102D C U
A1
5
B1
8
VCCA
3
VCCB
7
OE
6
GND
2
A2
4
B2
1
TXC+
DVI_DSEL
DVI_DATA15
TFADJ
DVI_DATA11
DVI_VSYNC
TXD1+
TVDD
DVI_DATA14
TXD0+
RP1C 103 14
DVI_DATA12
DVI_DATA17
TXD 2-
DVI _PVD D
410_N C
DVI_DATA7
DVI_DATA8
TXC-
DKEN
DVI_DVDD
DVI_HSYNC
C158 0.1uF,10V
TXD1-
DVI_DATA6
DVI_PUP
DVI_DATA9
DVI _VR EF
HTPLG
DVI_DATA13
C1 59 0.1uF ,10V
P12
CONN_HDMI
DAT2+
1
DAT2-
3
DAT2_S
2
DAT1+
4
DAT1_S
5
DAT1-
6
DAT0+
7
DAT0_S
8
DAT0-
9
CLK+
10
CLK-
12
CLK_S
11
CEC
13
NC
14
SCL
15
SDA
16
DDC/CEC GND
17
+5V
18
HPLG
19
MTG1
MTG1
MTG2
MTG2
MTG3
MTG3
MTG4
MTG4
RP1D 104 13
R90 10K
L7 F ERRITE, MMZ1608R301A1 2
DDC I2C Interface
Adjusted f or .9V
Internal 10K Pullups.
L8 F ERRITE, MMZ1608R301A1 2
R87
510
L9 F ERRITE, MMZ1608R301A1 2
C152 0.1uF,10V
RP1E 105 12
DK3
C157 0.1uF,10V
DK1
DK2
100Ma
DVI_DATA18
C155 0.1uF,10V
U4AProc essor
DSS_D0
AG22
DSS_D1
AH22
DSS_D2
AG23
DSS_D3
AH23
DSS_D4
AG24
DSS_D5
AH24
DSS_D6
E26
DSS_D7
F28
DSS_D8
F27
DSS_D9
G26
DSS_D10
AD28
DSS_D11
AD27
DSS_D12
AB28
DSS_D13
AB27
DSS_D14
AA28
DSS_D15
AA27
DSS_D16
G25
DSS_D17
H27
DSS_PCLK
D28
DSS_HSY NC
D26
DSS_VSYNC
D27
DSS_ACBIAS
E27
DSS_D18
H26
DSS_D19
H25
DSS_D20
E28
DSS_D21
J26
DSS_D22
AC27
DSS_D23
AC28
DSS_D18
AH26
DSS_D19
AG26
DSS_D20
AF18
DSS_D21
AF19
DSS_D22
AE21
DSS_D23
AF21
Figure 44. DVI-D Interface
One of the main changes in the DSS area on the –xM is the change of the DSS pin usage.
The processor requires that different pins be used if 720p resolutions are required. These
pins are different than those that are currently used on the Rev C4. The basic change
requires that the DSS_D0-D5 need to be moved to the pins that normally carry the
DSS_D18-D23 leads. In this case, the signals for DSS_D18-D23 need to be moved to
other pins. Reflected in Figure 44 are four resistor packs inside either Red or Blue boxes.
These are the loading options to enable the new mode used by the –xM or the legacy
mode used by the Rev C4. The resistor packs in the RED boxes are installed and the
BLUE boxes are not installed on the –xM to support the 720p resolution.
For legacy operation, you would need to install the BLUE boxes and leave out the RED
boxes. The SW will take care of this automatically, but you may want to do this if your
design were to need to work in the legacy mode.
- BeagleBoard-xM Rev A2 1
- System Reference Manual 1
- Table of Contents 5
- Figures 9
- Tables 11
- 1.0 Introduction 13
- 2.0 Change History 15
- 2.2.2 Software Changes 16
- 4.0 BeagleBoard Overview 17
- Figure 2. USB Y-Cable 21
- 6.0 Product Contents 28
- 7.0 BeagleBoard Hookup 30
- BEAGLEBOARD 36
- VOLT_ERR 45
- 8.2.1 Detection 46
- 8.2.2 Indication 46
- 8.2.3 Shutdown 46
- USB_CLIENT / 47
- OTG PORT 47
- DC_POWER 47
- 8.3.1 USB DC Source 48
- 8.3.2 Wall Supply Source 48
- 8.3.3 DC Source Control 48
- 8.3.4 AUX 3.3V Supply 49
- Figure 25. Main Power Rails 55
- 8.7.6 VOCORE_1V3 56
- 8.7.7 VDD2 56
- 8.8.1 VDD_PLL2 57
- 8.8.2 VDD_PLL1 58
- 8.8.3 VDAC_1V8 58
- 8.8.10 EXP_VDD 60
- 8.9.1 Boot Configuration 60
- 8.9.2 RTC Backup Battery 60
- 8.9.3 Power Sequencing 61
- Figure 27. Power Sequencing 61
- 8.9.4.3 User Reset 63
- 8.9.4.4 PWRON 63
- 8.9.5 mSecure Signal 63
- 8.10.1 Overview 64
- 8.10.2 SDRAM Bus 65
- 8.10.3 GPMC Bus 65
- Processor 66
- 8.10.9 GPIO Mapping 69
- 8.10.10 Interrupt Mapping 69
- Figure 33. POP Memory 70
- Figure 34. System Clocks 70
- 8.12.1 32KHz Clock 71
- 8.12.2 26MHz Clock 71
- 8.12.2.1 26MHz Source 71
- 8.12.2.2 TPS65950 Setup 71
- 8.12.2.3 Processor 26MHz 71
- 8.12.3 McBSP_CLKS 72
- 8.13.1 USB OTG Overview 72
- 8.13.2 USB OTG Design 73
- Figure 35. USB OTG Design 73
- 8.13.3 OTG ULPI Interface 73
- 8.13.3.2 TPS65950 Interface 74
- 8.13.4 OTG Charge Pump 74
- 8.13.5 OTG USB Connector 75
- 8.13.6 OTG USB Protection 75
- 8.14.1 Power 76
- 8.14.2 HS USB PHY 77
- Figure 38. USB PHY Design 78
- 8.14.3 USB HUB 79
- Figure 39. USB HUB Design 80
- 8.14.4 USB Port Connectors 81
- 8.14.5 Ethernet 82
- 8.15.1 microSD Power 83
- 8.15.2 Processor Interface 83
- 8.15.3 Card Detect 84
- Figure 43. Audio Circuitry 85
- 8.16.3 Audio Output Jack 86
- 8.16.4 Audio Input Jack 86
- Figure 44. DVI-D Interface 87
- 8.17.2 LCD Power 89
- 8.17.3 TFP410 Power 89
- 8.17.4 TFP410 Framer 89
- 8.17.6.8 DVI to VGA 93
- Table 16. P11 LCD Signals 93
- Table 17. P13 LCD Signals 94
- 8.20.4 Camera Modules 100
- Figure 47. Camera Modules 100
- 8.21.1 Processor Interface 101
- 8.21.2 Level Translator 101
- 8.21.3 RS232 Transceiver 102
- 8.21.4 Connector 102
- 8.22.1 Power Indicator 103
- 8.22.2 PMU Status Indicator 103
- Figure 49. Indicator Design 103
- 8.22.3 User Indicators 104
- 8.22.4 HUB Power Indicator 104
- Figure 50. JTAG Interface 105
- 8.23.1 Processor Interface 105
- Table 21. JTAG Signals 105
- 8.23.2 JTAG Connector 106
- 8.24.1 Processor Interface 106
- 8.24.2 Expansion Signals 108
- 8.24.3 Power 109
- 8.24.4 Reset 109
- 8.24.5 Power Control 109
- Table 24. P11 GPIO Signals 110
- MUX:0 MUX:2 MUX:4 110
- Table 25. P13 GPIO Signals 110
- 8.26.1 MCBSP5 Signals 111
- 8.26.2 MMC3 Signals 112
- 8.26.3 ETK Signals 112
- 8.26.4 HSUSB1 Signals 113
- 8.26.5 Alternate Clock 113
- 8.26.6 HDQ 1-Wire 113
- 8.26.7 ADC 113
- 8.26.8 GPIO Signals 114
- 8.26.9 DMAREQ 114
- Figure 52. Power Connector 115
- Figure 56. DVI-D Connector 118
- DVI-D interface itself 118
- Figure 57. DVI-D Cable 119
- Figure 58. DVI-D Cable 119
- 9.5.1 Connector Pinout 120
- Table 33. P11 LCD Signals 120
- Table 34. P13 LCD Signals 121
- 9.5.2 Camera 122
- Figure 60. Camera Connector 123
- Figure 61. Camera Module 123
- 9.5.3 Audio McBSP2 Port 124
- 9.5.6 Mounting Scenarios 127
- Figure 66. Audio In Plug 128
- Figure 68. Audio Out Plug 129
- Table 39. JTAG Signals 130
- 9.9.1 Battery 132
- Figure 73. Optional Battery 132
- 9.9.2 Battery Installation 132
- Figure 75. Resistor R65 133
- Table 41. DC Power Supplies 135
- Figure 76. DC Power Supply 135
- Figure 79. USB to Bluetooth 138
- 11.0 Mechanical Information 140
- 11.2.1 Mounting Method 141
- 11.2.2 Expansion EEPROM 143
- Table 46. Voltages 145
- 12.1.1 Signal Access Points 146
- Table 47. Troubleshooting 147
- 13.0 Known Issues 148
- 15.0 Schematics 151
- 16.0 Bills of Material 163
- 17.0 PCB Information 164
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